This invention relates to multi-level logic circuits and in particular, those multi-logic level circuits that operate with a single clock pulse.
Dynamic multi-level logic circuits that are manufactured by the metal oxide silicon process require a multiphase clock to insure the proper implementation of the desired logic function. The implementing of a priority multilevel logic function requires the partitioning of the logic into time slots and then assigning the required number of clock phases to cover the worse case or maximum number of logic levels that are to be implemented. The phases of the clock are generated by dividing a clock signal from a basic signal source down. This results in multiple phases of clock signals, typically all phases being related to a basic source frequency that is divided down by one, two, four, etc., which means that all the phases of the clock are multiples of the basic source frequency. In this scheme, the frequency of operation is increased until one phase, which is normally only one, becomes critical. When this happens, many of the logic levels are left with redundant time available to complete the decision operation.
Although MOS circuits are considered economical to manufacture, because of the necessity of requiring separate clock phases for precharging and evaluation of the logic levels, these circuits are normally not utilized in many high speed circuits.